Design & Reuse
Catalog of SIP Cores
System on Chip design resources
404 IP
401
0.0
TSMC CLN85LP 90nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
402
0.0
TSMC CLN85LP 90nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
403
0.0
TSMC CLN85LP 90nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
404
0.0
TSMC PLL _ Clock Generator / Clock Synthesizer / Phase-Locked Loop, (Fractional / Integer)
The ARKCHIPS PLL is a versatile and stable general-purpose frequency synthesizer with phase synchronization (de-skew) Phase-Locked Loop (PLL) : feed...